1. The Field of the Invention
The present invention relates to analog integrated circuit design, and more particularly, to direct conversion receivers having reduced Direct Current (DC) offset.
2. Background and Related Art
Electrical signals have proven to be an effective means of conveying data from one location to another. The further a signal is transmitted, however, the greater the decay in the signal and the greater the chance for irreversible loss in the data represented by the signal. In order to guard against this signal decay, the core electrical signal that represents the data (i.e., the baseband signal) may be modulated or superimposed on a carrier wave in the Radio Frequency (RF) frequency spectrum.
In order to properly interpret the signal, conventional RF receivers extracts the baseband signal from the received signal. The data represented by the extracted baseband signal may then be interpreted by other downstream circuitry. In order to perform this extraction, typical receivers include circuitry which first converts the received radio frequency modulated signal into an intermediate frequency (“IF”) signal. This intermediate frequency signal is then converted into the baseband signal for further data processing. Receiver architectures that convert through the intermediate frequency are often called “heterodyne” receiver architectures. Naturally, circuit elements (called “IF components”) are required in order to deal with the intermediate conversion to and from the intermediate frequency.
It is desirable to reduce the cost, size, and power consumption of a particular receiver architecture design for strategic marketing of the receiver. This is particularly true of wireless RF receivers since those receivers are often portable and run on battery power. One technology developed in order to reduce RF receiver cost, size, and power consumption is called “direct conversion.” Direct conversion refers to the direct conversion of RF modulated signals into corresponding baseband signals without requiring conversion through the intermediate frequency. Such direct conversion receiver architectures are often also called “zero-IF,” “synchrodyne,” or “homodyne” receiver architectures.
FIG. 5 illustrates a conventional direct conversion circuit 500 in accordance with the prior art. The circuit 500 includes an antenna 501 which receives the RF modulated signal. The antenna 501 then provides the received signal to an amplifier 502 which amplifies the signal for further processing. The amplifier 502 may be, for example, an RF low noise amplifier.
The amplified signal is then split into two branches, an “in-phase” branch 510, and a “quadrature-phase” branch 520. Each branch includes a mixer that initially receives the amplified signal. For instance, the in-phase branch 510 includes an in-phase mixer 511, and the quadrature-phase branch 520 includes a quadrature-phase mixer 521. A local oscillator 530 provides a sine or square wave signal as a control signal to each of the mixers. Each mixer is configured to nonlinearly process the amplified signal and control signal, resulting in output signal components at frequencies equal to the sum and difference of amplified signal and control signal frequencies, plus higher-order components at other frequencies. The circuit includes a 90-degree phase shifter 531 which causes the control signal for the quadrature-phase mixer 521 to be 90 degrees out of phase with the control signal for the in-phase mixer 511.
The signal from the in-phase mixer 511 is then passed through a low pass filter 512 to a baseband amplifier 513 to complete the extraction of the baseband (difference frequency) signal from the received signal as far as the in-phase branch 510 is concerned. Likewise, the signal from the quadrature-phase mixer 521 is passed through a low pass filter 522 to a baseband amplifier 523 to complete the extraction of the baseband (difference frequency) signal as far as the quadrature-phase branch is concerned. The in-phase and quadrature-phase baseband signals are then processed by signal processing circuitry 550.
The direct conversion circuit of FIG. 5 does not convert through an intermediate frequency and thus there are no IF components needed to deal with an intermediate conversion. Consequently, the direct conversion circuit of FIG. 5 is smaller, and requires less power than conventional heterodyne receiver architectures. Furthermore, the direct conversion circuit does not have to deal with image suppression as much as do heterodyne receivers.
However, there are some performance issues for the direct conversion circuit of FIG. 5 that limit its practical implementation. In particular, conventional direct conversion circuits suffer from Direct Current (DC) offset. The DC offset in conventional direct conversion receivers has two primary origins. One primary origin is the down-converting mixer itself in which the DC offset are self-mixing DC products present at the mixer outputs. The other primary DC offset origin is in active elements, such as highly sensitive amplifiers, that operate on the down-converted baseband signal. Such DC offsets can swamp out the much weaker desired signal.
Direct conversion circuits have many advantages in terms of size, power consumption, and cost to manufacture. In addition, direct conversion circuits also have good selectivity and the mitigation of an image frequency. However, as mentioned above, many direct conversion circuits also have some drawbacks in the form of increased DC offset. According, what would be advantageous are direct conversion circuits that have reduced DC offset.